Computer systems and integrated circuit processors exist which implement transactions with the dispatch and receipts of packets. Request packets define an operation to be performed and response packets indicate that a request has been received. The integrated circuit processor can comprise a plurality of functional modules connected to a packet router for transmitting and receiving the request and response packets. In such a system, it is necessary to arbitrate between requests received from the functional modules for controlling the flow of packets on the packet router (whether request or response packets). Typically, multiple functional modules are able to access the same bus or the same part of the system which leads to competition for that bus or for the same destination or target modules. The complexity of the arbitration mechanism is a function of the number of devices in the system and the arbitration algorithm which is used.
As the size and clock frequency of such systems, in particular integrated systems, increases, and the complexity of the arbitration function increases, the time required to make an arbitration decision for accesses to resources such as the system bus or target modules becomes critical. In many systems, it is not possible to make an arbitration decision and effect a packet transfer in a single clock cycle. This leads to a drop in potential performance as gaps are inserted increasing the latency between a request for packet transfer being made and the packet transfer actually being implemented.
It is an aim of the present invention to reduce the impact of arbitration decision latency on a system.